Information for S3 Chipset Users : Supported hardware
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1. Supported hardware

The current S3 Server supports the following S3 chipsets: 911, 924, 801/805, 928, 732 (Trio32), 764, 765, 775, 785 (Trio64*), 864, 868, 964, 968 and M65 (Aurora64V+). The S3 server will also recognise the 866, but it has not been tested with this chipset. If you have any problems or success with these, please report it to us.

Nevertheless, this is not enough to support every board using one of these chipsets. The following list contains some data points on boards that are known to work. If your card is similar to one of the described ones, chances are good it might work for you, too.

S3 801/805, AT&T 20C490 (or similar) RAMDAC

8 and 15/16 bpp

Note: Real AT&T20C490 RAMDACs should be automatically detected by the server. For others which are compatible, you need to provide a `Ramdac "att20c490"' entry in your XF86Config.

Real AT&T 20C490 or 20C491 RAMDACs work with the "dac_8_bit" option. Some clones (like the Winbond 82C490) do not.

The Orchid Fahrenheit 1280+ VLB may require `Option "nolinear"'.

S3 805 VLB, S3 GENDAC (RAMDAC + clock synthesizer)

8 and 15/16 bpp

 ClockChip "s3gendac"
 RamDac    "s3gendac"

S3 801/805, AT&T 20C490 RAMDAC, ICD2061A Clockchip

8 and 15/16 bpp

Note: Real AT&T20C490 RAMDACs should be automatically detected by the server. For others which are compatible, you need to provide a `Ramdac "att20c490"' entry in your XF86Config.

 ClockChip "icd2061a"
 RamDac    "att20c490"
 Option    "dac_8_bit

S3 805, Diamond SS2410 RAMDAC, ICD2061A Clockchip

8 and 15bpp(*) only.

requires `Option "nolinear"'

(*) The SS2410 RAMDAC is reportedly compatible with the AT&T20C490 in 15bpp mode. To make the server treat it as an AT&T20C490, you need to provide a `Ramdac "att20c490"' entry in your XF86Config.

S3 801/805, Chrontel 8391 Clockchip/Ramdac

8 and 15/16 bpp.

The 8391 is compatible with the AT&T 20C490 RAMDAC

 ClockChip "ch8391"
 Ramdac    "ch8391"
 Option    "dac_8_bit"

S3 928, AT&T 20C490 RAMDAC

8 and 15/16 bpp

Note: Real AT&T20C490 RAMDACs should be automatically detected by the server. For others which are compatible, you need to provide a `Ramdac "att20c490"' entry in your XF86Config. Also, the server's RAMDAC probe reportedly causes problems with some of these boards, and a RamDac entry should be used to avoid the probe.

Real AT&T 20C490 or 20C491 RAMDACs work with the "dac_8_bit" option. Some clones (like the Winbond 82C490) do not.

S3 928, Sierra SC15025 RAMDAC, ICD2061A Clockchip

8, 15/16 and 24(32) bpp

Supports 8bit/pixel RGB in 8bpp and gamma correction for 15/16 and 24bpp modes

24 bpp might get ``snowy'' if the clock is near the limit of 30MHz. This is not considered dangerous, but limits the usability of 24 bpp.

D-step (or below) chips cannot be used with a line width of 1152; hence the most effective mode for a 1 MB board is about 1088x800x8 (similar to 2 MB, 1088x800x16).

 ClockChip "icd2061a"

S3 928, Bt9485 RAMDAC, ICD2061A Clockchip

8, 15/16 and 24(32) bpp

Supports RGB with sync-on-green if "sync_on_green" option is provided and board jumper is set for BNC outputs.

VLB linear addressing now occurs at 0x7FCxxxxx so that 64MB or more main memory can be supported without losing linear frame buffer access.

 ClockChip "icd2061a"
 Option    "stb_pegasus"

S3 928, Bt485 RAMDAC, SC11412 Clockchip

8, 15/16 and 24(32) bpp 

 ClockChip "SC11412"
 Option    "SPEA_Mercury"

S3 928, Bt485 RAMDAC, ICD2061A Clockchip

8, 15/16 and 24(32) bpp

 ClockChip "icd2061a"
 Option    "number_nine"

S3 928, Ti3020 RAMDAC, ICD2061A Clockchip

8, 15/16 and 24(32) bpp

Supports RGB with sync-on-green

 ClockChip "icd2061a"
 Option    "number_nine"

S3 864, AT&T20C498, ICS2494 Clockchip

The ICS2494 is a fixed frequency clockchip, you have to use X -probeonly (without a Clocks line in XF86Config) to get the correct clock values.

8, 15/16 and 24(32) bpp

S3 864, AT&T20C498 or STG1700 RAMDAC, ICD2061A or ICS9161 Clockchip

8, 15/16 and 24(32) bpp

 ClockChip "icd2061a"

S3 864, 20C498 or 21C498 RAMDAC, ICS2595 Clockchip

8, 15/16 and 24(32) bpp

Clockchip support is still sometimes flaky and on some machines problems with the first mode after startup of XF86_S3 or after switching back from VT have been seen; switching to next mode with CTRL+ALT+``KP+'' and back seems to solve this problem.

Interlaced modes don't work correctly.

Mirage P64 with BIOS 4.xx uses the S3 SDAC. 

 ClockChip "ics2595"

S3 864, S3 86C716 SDAC RAMDAC and Clockchip

8, 15/16 and 24 bpp

S3 864, ICS5342 RAMDAC and Clockchip

8, 15/16 and 24 bpp

 ClockChip "ics5342"
 Ramdac    "ics5342"

S3 864, AT&T21C498-13 RAMDAC, ICD2061A Clockchip

8, 15/16, 24(32) bpp

 ClockChip "icd2061a"
 Option    "number_nine"

S3 964, AT&T 20C505 RAMDAC, ICD2061A Clockchip

8, 15/16, 24(32) bpp

 ClockChip "icd2061a"
 Ramdac    "att20c505"

S3 964, Bt485 RAMDAC, ICD2061A Clockchip

8, 15/16, 24(32) bpp

 ClockChip "icd2061a"

S3 964, Bt9485 or AT&T 20C505 RAMDAC, ICS9161a Clockchip

8, 15/16, 24(32) bpp

 ClockChip "ics9161a"
 Option    "SPEA_Mercury"

S3 964, Ti3020 RAMDAC, ICD2061A Clockchip

8, 15/16, 24(32) bpp

 ClockChip "icd2061a"

S3 964, Ti3025 RAMDAC, Ti3025 Clockchip

8 bpp, 15, 16 and 24(32) bpp

There are some known problems with the GXE64 Pro support, including some image shifting/wrapping at 15/16/24 bpp.

We have found that #9 no longer support the GXE64 Pro at 1600x1200. They do however have a new (and more expensive) board called the GXE64Pro-1600 which uses a 220MHz RAMDAC instead of 135MHz part used on the other boards.

S3 764 (Trio64)

8/15/16/24 bpp

Note: The Trio64 has a builtin RAMDAC and clockchip, so the server should work with all Trio64 cards, and there is no need to specify the RAMDAC or clockchip in the XF86Config file.

S3 732 (Trio32)

8/15/16/24 bpp

Note: The Trio32 has a builtin RAMDAC and clockchip, so the server should work with all Trio32 cards, and there is no need to specify the RAMDAC or clockchip in the XF86Config file.

S3 868, S3 86C716 SDAC RAMDAC and Clockchip

8/15/16/24 bpp

S3 868, AT&T 20C409 RAMDAC and Clockchip

8/15/16/24 bpp

Note: pixelmultiplexing is not supported yet, therefore limited maximum dot clock for 8bpp (currently 67.5MHz, should be changed to 100MHz if pixmux isn't fixed prior to release)

S3 968, Ti3026 RAMDAC, Ti3026 Clockchip

8/15/16/24 bpp

S3 968, Ti3026 RAMDAC, ICS9161A Clockchip

8/15/16/24 bpp

Note: clock doubling doesn't work, yet, therefore the maximum usable dot clock is limited to about 120MHz.

S3 964, IBM RGB 514/524/525/528 RAMDAC & Clockchip

8/15/16/24 bpp

 s3RefClk   50
 DACspeed  170
 Option  "slow_vram"

S3 968, IBM RGB 514/524/525/528 RAMDAC & Clockchip

8/15/16/24 bpp

ELSA Winner 2000PRO/X-8 (S3 968, 8MB VRAM, 220MHz for 32bpp)

The server has only been tested for "revision C" of this card (guess the serial number should start with C, but not sure since mine says Ser.No. A-0000.000.000;) which have an IBM RGB528A note the A; can't be probed though)

depending on the mode line etc there may be some display distortions like:

  1. many long horizontal lines/stripes
  2. pixel jitter or short horizontal stripes like snow all over the screen
  3. Like 2., but only when doing graphics ops (like opaque move of windows).
  4. additional pixel at the left display edge and some missing pixels at the right edge.
All of these problems can be fixed by small adjustments to the mode line (best to run `xvidtune' and make these adjustments interactively). E.g., for the first three problems, shift the display left or right a few steps. For the last problem, increasing HSyncEnd (making the hsync pulse longer) solves the problem. In some cases, a significant increase in the sync pulse width is needed, and rarely, it needs to be shortened (by decreasing HSyncEnd).

In rare cases, InvertVCLK and/or EarlySC may need to be adjusted, followed by an adjustment of BlankDelay (see the bottom line of xvidtune).

If you see any of these problems, please contact [email protected], and send details of:

Information for S3 Chipset Users : Supported hardware
Previous: Information for S3 Chipset Users
Next: 16bpp and 32bpp